1. Field of the Invention
The present invention relates to a semiconductor device for driving a heat generator used in an ink jet head or a thermal head which is mounted on a printer such as a copying machine, facsimile equipment or the like.
2. Description of the Related Art
A thermal head is provided with a heat generator comprising either a thin film resistor or a thick film resistor.
Alternatively, there are ink jet heads which are capable of reproducing excellent images which include a head which discharges ink by using thermal energy. This head is also provided with a heat generator comprising a thin film resistor or the like.
A semiconductor device is used for driving such a heat generator. Known examples of such semiconductor devices include the devices disclosed in U.S. Pat. No. 4,429,321, and European Patent Laid-Open Nos. 0,378,439 and 0,440,459.
For example, the circuit shown in FIG. 1 is generally known as a matrix circuit for driving a 64-bit ink jet head. The matrix circuit shown in FIG. 1 has a switching circuit comprising 64 diodes 11, 12, . . . 18, . . . 81, 82, . . . 88 which are divided into 8 blocks for common lines and 8 blocks for segment lines. The blocks for the common lines are respectively provided with 8 switches Com1, Com2 . . . Com8, and the blocks for the segment lines are respectively provided with 8 0 switches Seg1, Seg2 . . . Seg8. Such a matrix circuit is generally provided on a silicon substrate SUB by a bipolar process.
However, if such a matrix circuit comprises pn-type diode switches disposed on a silicon substrate, error is produced between respective common switches or segment switches. It is thus necessary that diodes each comprise an npn transistor and are arranged on a substrate by collector-base short circuiting. Such a matrix circuit also has the following problems to be solved:
(1) The process is complicated due to using bipolar process;
(2) Since a large current (200 mA) flows through each diode switch, and a current of about 1.6 mA flows through the external switches of each block for the common lines when the 8 external switches for the segment lines are simultaneously turned on, the arrangement of the external switches is complicated.
In order to solve the above two problems, a matrix circuit has been proposed in which an npn transistor switching circuit is used in place of the diode switching circuit shown in FIG. 1, as shown in FIG. 2. However, this matrix circuit has the limitation noted below. The limitation is described below with reference to FIG. 3 which shows an equivalent circuit for one bit of the matrix circuit shown in FIG. 2.
In FIG. 3, assuming that current I is 200 mA, and the forward current amplification factor of a transistor Tr11 is 100, the following equations are established: EQU I=I.sub.C +I.sub.B EQU I.sub.C =.beta.I.sub.B
The potential at point (A) shown in FIG. 3 is V.sup.+ -I.sub.C .times.r.sub.SC, and the potential at point (B) is V.sup.+ -I.sub.B .times.r.sub.B under the condition in that a parasitic pnp transistor is not turned on. The ideal potential V.sub.BE of the parasitic pnp transistor preferably satisfies the following condition: EQU V.sub.BE =I.sub.C .times.r.sub.SC -I.sub.B .times.r.sub.B .ltoreq.0
The relation, I.sub.C .times.r.sub.SC &lt;I.sub.B .times.r.sub.B, is thus required. In order to satisfy this relation it is necessary to decrease the voltage drop caused by the collector current I.sub.C, which is characteristic of an npn transistor, and decrease both the collector series resistance r.sub.SC and the forward current amplification factor .beta. of the transistor Tr11,
In the matrix circuit comprising the npn transistor switching circuit shown in FIG. 2, although the current flowing through a common external switch 1 (Com1) is decreased, as compared with the diode switching circuit shown in FIG. 1, the base current I.sub.B flowing through the common external switch 1 is increased to some extent due to the limitations on the characteristics of a transistor. Thus the matrix circuit shown in FIG. 2 still has the problem that the configuration of the external switching circuit for the common lines must be complicated.
The inventors thus determined that the npn transistor switches shown in FIGS. 2 and 3 be replaced by nMOS transistor switches. Since the external switching circuit for the common lines controls the nMOS transistor switches alone, the configuration of the external switching circuit for the common lines can be simplified. However, this Circuit has the problem that since the potential V.sup.+ is 30 to 40 V, when a generally known nMOS transistor is used, the electric field strength between a source and a drain is increased, and hot carriers thus occur, thereby causing changes in the threshold value (V.sub.th) and the transconductance of the nMOS transistor due to the entrance of the hot carriers into a gate oxide film. In addition, since the pn junction formed by an n-type drain and a p-type well is reversely biased, avalanche breakdown occurs.